The disclosure is generally directed to a data processing system having a weakly-ordered memory system and, more particularly, to techniques for implementing barriers to efficiently support cumulativity in a data processing system having a weakly-ordered memory system.
In computing, a memory model describes the interactions of threads through memory and how threads share data. Memory barriers are widely utilized in data processing systems that are configured to perform out-of-order program execution, which refers to reordering of memory operations (i.e., load and store operations) for execution. A barrier instruction (barrier) can, for example, cause all load instructions (loads) and store instructions (stores) prior to the barrier to be committed prior to any loads and stores issued following the barrier. Some architectures provide separate acquire and release barriers that address the visibility of read-after-write operations from the point of view of a reader or writer, respectively. Still other architectures provide separate barriers to control ordering between different combinations of operations targeting system memory and input/output (I/O) memory.